0xWheatyz/chicken-coop-door
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chore(kicad): migrate project files to kicad 10 format

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Open and save the board, project, and project-local state files under
KiCad 10. Bumps board format version 20241229 -> 20260206 with the new
tenting/covering/plugging/capping/filling stackup directives, drops the
removed HPGL plot params, and adds the KiCad 10 schema additions to the
project file (component class settings, IPC-2581 revision fields, ERC
rule keys, tuning-profile DRC keys, netclass meta version 5). Also
captures live editor UI state (active layer, column widths, hierarchy
collapsed list) in the .kicad_prl.

Constraint: Project is now opened with KiCad 10 - cannot be downgraded
Confidence: high
Scope-risk: broad
Directive: Do not edit these files with KiCad 9.x - format is one-way
This commit is contained in:
0xWheatyz
2026-05-14 22:34:10 -04:00
parent afd63000b5
commit 0e18a10bdb
3 changed files with 7106 additions and 5532 deletions
Download Patch File Download Diff File Expand all files Collapse all files
firstpcb.kicad_pcb
+7028 -5512
View File
File diff suppressed because it is too large Load Diff
firstpcb.kicad_prl
+18 -13
View File
@@ -1,6 +1,6 @@
{
"board": {
"active_layer": 21,
"active_layer": 2,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
@@ -15,6 +15,7 @@
"vias": 1.0,
"zones": 0.6
},
"prototype_zone_fills": false,
"selection_filter": {
"dimensions": true,
"footprints": true,
@@ -54,6 +55,7 @@
"zone_display_mode": 0
},
"git": {
"integration_disabled": false,
"repo_type": "",
"repo_username": "",
"ssh_key": ""
@@ -88,16 +90,16 @@
9
],
"col_widths": [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
69,
71,
94,
78,
84,
97,
85,
80,
42,
666
],
"custom_group_rules": [],
"expanded_rows": [],
@@ -106,16 +108,18 @@
"filter_text": "",
"group_by_constraint": false,
"group_by_netclass": false,
"show_time_domain_details": false,
"show_unconnected_nets": false,
"show_zero_pad_nets": false,
"sort_ascending": true,
"sorting_column": 0
"sort_ascending": false,
"sorting_column": 7
},
"open_jobsets": [],
"project": {
"files": []
},
"schematic": {
"hierarchy_collapsed": [],
"selection_filter": {
"graphics": true,
"images": true,
@@ -123,6 +127,7 @@
"lockedItems": false,
"otherItems": true,
"pins": true,
"ruleAreas": true,
"symbols": true,
"text": true,
"wires": true
firstpcb.kicad_pro
+60 -7
View File
@@ -3,6 +3,8 @@
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_barcodes": false,
"apply_defaults_to_fp_dimensions": false,
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
@@ -77,6 +79,7 @@
"extra_footprint": "warning",
"footprint": "error",
"footprint_filters_mismatch": "ignore",
"footprint_symbol_field_mismatch": "warning",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
@@ -94,6 +97,7 @@
"mirrored_text_on_front_layer": "warning",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"missing_tuning_profile": "warning",
"net_conflict": "warning",
"nonmirrored_text_on_back_layer": "warning",
"npth_inside_courtyard": "ignore",
@@ -113,9 +117,12 @@
"too_many_vias": "error",
"track_angle": "error",
"track_dangling": "warning",
"track_not_centered_on_via": "ignore",
"track_on_post_machined_layer": "error",
"track_segment_length": "error",
"track_width": "error",
"tracks_crossing": "error",
"tuning_profile_track_geometries": "ignore",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
@@ -224,17 +231,28 @@
"zones_allow_external_fillets": false
},
"ipc2581": {
"bom_rev": "",
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
"mpn": "",
"sch_revision": ""
},
"layer_pairs": [],
"layer_presets": [],
"viewports": []
},
"boards": [],
"component_class_settings": {
"assignments": [],
"meta": {
"version": 0
},
"sheet_component_classes": {
"enabled": false
}
},
"cvpcb": {
"equivalence_files": []
},
@@ -424,11 +442,14 @@
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"field_name_whitespace": "warning",
"footprint_filter": "ignore",
"footprint_link_issues": "warning",
"four_way_junction": "ignore",
"global_label_dangling": "warning",
"ground_pin_not_ground": "warning",
"hier_label_mismatch": "error",
"isolated_pin_label": "warning",
"label_dangling": "error",
"label_multiple_wires": "warning",
"lib_symbol_issues": "warning",
@@ -441,9 +462,9 @@
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_connected": "ignore",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"same_local_global_label": "warning",
"similar_label_and_power": "warning",
@@ -451,6 +472,7 @@
"similar_power": "warning",
"simulation_model_issue": "ignore",
"single_global_label": "ignore",
"stacked_pin_name": "warning",
"unannotated": "error",
"unconnected_wire_endpoint": "warning",
"undefined_netclass": "error",
@@ -483,13 +505,14 @@
"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 4
"version": 5
},
"net_colors": null,
"netclass_assignments": null,
@@ -516,6 +539,10 @@
},
"schematic": {
"annotate_start_num": 0,
"annotation": {
"method": 0,
"sort_order": 0
},
"bom_export_filename": "${PROJECTNAME}.csv",
"bom_fmt_presets": [],
"bom_fmt_settings": {
@@ -587,6 +614,7 @@
"sort_asc": true,
"sort_field": "Reference"
},
"bus_aliases": {},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
@@ -594,6 +622,7 @@
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"hop_over_size_choice": 0,
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
@@ -615,8 +644,17 @@
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"meta": {
"version": 0
},
"model_mode": 4,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"reuse_designators": true,
"space_save_all_events": true,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
@@ -625,13 +663,28 @@
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
"subpart_id_separator": 0,
"top_level_sheets": [
{
"filename": "firstpcb.kicad_sch",
"name": "firstpcb",
"uuid": "4ce690e5-6d5b-4693-bd2e-f4090f26df1f"
}
],
"used_designators": "",
"variants": []
},
"sheets": [
[
"4ce690e5-6d5b-4693-bd2e-f4090f26df1f",
"Root"
"firstpcb"
]
],
"text_variables": {}
"text_variables": {},
"tuning_profiles": {
"meta": {
"version": 0
},
"tuning_profiles_impedance_geometric": []
}
}