0xWheatyz
24d76b1fff
Insets uniformly 3.00 mm from each board edge. Hole pattern is 75.00 mm (X) x 54.00 mm (Y) center-to-centre on the 81 x 60 mm board. Hole specs per location: MH1 (63, 43) - top-left MH2 (138, 43) - top-right MH3 (63, 97) - bottom-left MH4 (138, 97) - bottom-right drill 2.2 mm (M2 medium-fit clearance), copper keep-out 4.0 mm dia, NPTH, no solder-mask opening. Constraint: M2 clearance hole, NPTH (no electrical connection) Constraint: board outline gr_rect (60,40)-(141,100) -> 81 x 60 mm Rejected: 2.5 mm inset | pad edge sits exactly on board edge clearance min Rejected: solder-mask opening on the pad | ESP32 silk at y=96.36 near MH3 produced two silk_over_copper warnings; bare drill (no mask opening) keeps DRC clean at the cost of less-visible holes Rejected: putting holes outside Edge.Cuts as silkscreen markers | user asked for real mounting holes, not indicators Confidence: high Scope-risk: narrow Directive: hole positions are coupled to the board outline -- if the outline changes, the 3.00 mm uniform inset must be recomputed
137 lines
2.5 KiB
Plaintext
137 lines
2.5 KiB
Plaintext
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