fix(pcb): resolve all DRC errors and unconnected pads

Drop 68 errors + 2 unconnected to 0 + 0. Key changes:

* U2 (TPS61088 RHL0020A) footprint: 8 internal "V" stitching vias
  re-numbered to 21 (thermal pad), drill widened 0.2032 -> 0.3 mm,
  pad 0.5 -> 0.6 mm, net set to GND with solid zone_connect. Two
  unnetted internal fp_poly graphics (F.Cu and F.Mask) deleted.
* U2 reference silk moved off the thermal pad (0,-3.5).
* Bridge segment added between U2 pad 20 (AGND) and pad 21 (PGND).
* MotorPower1 pad 2 and A4988 pad 8 set to solid zone_connect.
* +12V zone (B.Cu) connect_pads clearance 0.5 -> 0.2 mm and
  thermal_gap 0.5 -> 0.2 mm so fill can pass between A4988 pad
  rows and merge the orphan +12V island around pad 8.
* Orphan 0.1 mm F.Cu GND stub at (118.975, 75.325) removed.

Constraint: kicad-cli DRC clean is the acceptance bar
Constraint: U2 RHL0020A footprint edited inline only, source
  library copy untouched (causes a lib_footprint_mismatch warning)
Rejected: route a long F.Cu +12V trace pad8 -> U2 area | adds
  ~28 mm of routing across multiple components; clearance reduction
  is a one-line change with no clearance violations
Rejected: drop a stitching via near pad 8 | still leaves a small
  B.Cu island; zone clearance fix solves the root cause
Confidence: high
Scope-risk: moderate
Directive: do not raise the +12V zone clearance back to 0.5 mm
  without first re-routing pad 8 to merge the islands; otherwise
  the unconnected error returns
Not-tested: high-current behavior with 0.2 mm clearance on +12V
  (acceptable for the design's 12 V / sub-amp load, may need
  review if the load grows)

firstpcb.kicad_prl

@@ -1,6 +1,6 @@
 {
   "board": {
-    "active_layer": 2,
+    "active_layer": 0,
     "active_layer_preset": "",
     "auto_track_width": true,
     "hidden_netclasses": [],