Insets uniformly 3.00 mm from each board edge. Hole pattern is
75.00 mm (X) x 54.00 mm (Y) center-to-centre on the 81 x 60 mm board.
Hole specs per location:
MH1 (63, 43) - top-left
MH2 (138, 43) - top-right
MH3 (63, 97) - bottom-left
MH4 (138, 97) - bottom-right
drill 2.2 mm (M2 medium-fit clearance), copper keep-out 4.0 mm dia,
NPTH, no solder-mask opening.
Constraint: M2 clearance hole, NPTH (no electrical connection)
Constraint: board outline gr_rect (60,40)-(141,100) -> 81 x 60 mm
Rejected: 2.5 mm inset | pad edge sits exactly on board edge clearance min
Rejected: solder-mask opening on the pad | ESP32 silk at y=96.36
near MH3 produced two silk_over_copper warnings; bare drill (no mask
opening) keeps DRC clean at the cost of less-visible holes
Rejected: putting holes outside Edge.Cuts as silkscreen markers |
user asked for real mounting holes, not indicators
Confidence: high
Scope-risk: narrow
Directive: hole positions are coupled to the board outline -- if the
outline changes, the 3.00 mm uniform inset must be recomputed
Drop 68 errors + 2 unconnected to 0 + 0. Key changes:
* U2 (TPS61088 RHL0020A) footprint: 8 internal "V" stitching vias
re-numbered to 21 (thermal pad), drill widened 0.2032 -> 0.3 mm,
pad 0.5 -> 0.6 mm, net set to GND with solid zone_connect. Two
unnetted internal fp_poly graphics (F.Cu and F.Mask) deleted.
* U2 reference silk moved off the thermal pad (0,-3.5).
* Bridge segment added between U2 pad 20 (AGND) and pad 21 (PGND).
* MotorPower1 pad 2 and A4988 pad 8 set to solid zone_connect.
* +12V zone (B.Cu) connect_pads clearance 0.5 -> 0.2 mm and
thermal_gap 0.5 -> 0.2 mm so fill can pass between A4988 pad
rows and merge the orphan +12V island around pad 8.
* Orphan 0.1 mm F.Cu GND stub at (118.975, 75.325) removed.
Constraint: kicad-cli DRC clean is the acceptance bar
Constraint: U2 RHL0020A footprint edited inline only, source
library copy untouched (causes a lib_footprint_mismatch warning)
Rejected: route a long F.Cu +12V trace pad8 -> U2 area | adds
~28 mm of routing across multiple components; clearance reduction
is a one-line change with no clearance violations
Rejected: drop a stitching via near pad 8 | still leaves a small
B.Cu island; zone clearance fix solves the root cause
Confidence: high
Scope-risk: moderate
Directive: do not raise the +12V zone clearance back to 0.5 mm
without first re-routing pad 8 to merge the islands; otherwise
the unconnected error returns
Not-tested: high-current behavior with 0.2 mm clearance on +12V
(acceptable for the design's 12 V / sub-amp load, may need
review if the load grows)
Open and save the board, project, and project-local state files under
KiCad 10. Bumps board format version 20241229 -> 20260206 with the new
tenting/covering/plugging/capping/filling stackup directives, drops the
removed HPGL plot params, and adds the KiCad 10 schema additions to the
project file (component class settings, IPC-2581 revision fields, ERC
rule keys, tuning-profile DRC keys, netclass meta version 5). Also
captures live editor UI state (active layer, column widths, hierarchy
collapsed list) in the .kicad_prl.
Constraint: Project is now opened with KiCad 10 - cannot be downgraded
Confidence: high
Scope-risk: broad
Directive: Do not edit these files with KiCad 9.x - format is one-way
0xWheatyz
