Open and save the board, project, and project-local state files under
KiCad 10. Bumps board format version 20241229 -> 20260206 with the new
tenting/covering/plugging/capping/filling stackup directives, drops the
removed HPGL plot params, and adds the KiCad 10 schema additions to the
project file (component class settings, IPC-2581 revision fields, ERC
rule keys, tuning-profile DRC keys, netclass meta version 5). Also
captures live editor UI state (active layer, column widths, hierarchy
collapsed list) in the .kicad_prl.
Constraint: Project is now opened with KiCad 10 - cannot be downgraded
Confidence: high
Scope-risk: broad
Directive: Do not edit these files with KiCad 9.x - format is one-way
Extend board outline downward by 15mm to accommodate 6 new components:
U1 (L7805 voltage regulator), C1/C2/C3 (decoupling caps), R1/R2 (pull-down
resistors). Move bottom mounting holes to match new outline. Delete
incorrectly-routed traces for DIR, STEP, LIM_C and unconnected nets, then
re-route them correctly to ESP32 bottom-row pins. Add +5V and +12V power
traces on B.Cu with via for layer transition. Route MOTOR_CTRL on B.Cu to
avoid F.Cu conflicts.
Place U1, C1, C2, C3, R1, R2 in the left open area (x=73-86, y=48-60)
of the board outline. Add copper traces for +12V bus (U1 input to
existing +12V net via A4988), +5V bus (U1 output to ESP32 VIN and C2),
and limit switch signals (/LIM_A to SW1, /LIM_C to existing trace).
Remove orphaned net-0 segments and clear zone fills for regeneration.
0xWheatyz
