Insets uniformly 3.00 mm from each board edge. Hole pattern is
75.00 mm (X) x 54.00 mm (Y) center-to-centre on the 81 x 60 mm board.
Hole specs per location:
MH1 (63, 43) - top-left
MH2 (138, 43) - top-right
MH3 (63, 97) - bottom-left
MH4 (138, 97) - bottom-right
drill 2.2 mm (M2 medium-fit clearance), copper keep-out 4.0 mm dia,
NPTH, no solder-mask opening.
Constraint: M2 clearance hole, NPTH (no electrical connection)
Constraint: board outline gr_rect (60,40)-(141,100) -> 81 x 60 mm
Rejected: 2.5 mm inset | pad edge sits exactly on board edge clearance min
Rejected: solder-mask opening on the pad | ESP32 silk at y=96.36
near MH3 produced two silk_over_copper warnings; bare drill (no mask
opening) keeps DRC clean at the cost of less-visible holes
Rejected: putting holes outside Edge.Cuts as silkscreen markers |
user asked for real mounting holes, not indicators
Confidence: high
Scope-risk: narrow
Directive: hole positions are coupled to the board outline -- if the
outline changes, the 3.00 mm uniform inset must be recomputed
Drop 68 errors + 2 unconnected to 0 + 0. Key changes:
* U2 (TPS61088 RHL0020A) footprint: 8 internal "V" stitching vias
re-numbered to 21 (thermal pad), drill widened 0.2032 -> 0.3 mm,
pad 0.5 -> 0.6 mm, net set to GND with solid zone_connect. Two
unnetted internal fp_poly graphics (F.Cu and F.Mask) deleted.
* U2 reference silk moved off the thermal pad (0,-3.5).
* Bridge segment added between U2 pad 20 (AGND) and pad 21 (PGND).
* MotorPower1 pad 2 and A4988 pad 8 set to solid zone_connect.
* +12V zone (B.Cu) connect_pads clearance 0.5 -> 0.2 mm and
thermal_gap 0.5 -> 0.2 mm so fill can pass between A4988 pad
rows and merge the orphan +12V island around pad 8.
* Orphan 0.1 mm F.Cu GND stub at (118.975, 75.325) removed.
Constraint: kicad-cli DRC clean is the acceptance bar
Constraint: U2 RHL0020A footprint edited inline only, source
library copy untouched (causes a lib_footprint_mismatch warning)
Rejected: route a long F.Cu +12V trace pad8 -> U2 area | adds
~28 mm of routing across multiple components; clearance reduction
is a one-line change with no clearance violations
Rejected: drop a stitching via near pad 8 | still leaves a small
B.Cu island; zone clearance fix solves the root cause
Confidence: high
Scope-risk: moderate
Directive: do not raise the +12V zone clearance back to 0.5 mm
without first re-routing pad 8 to merge the islands; otherwise
the unconnected error returns
Not-tested: high-current behavior with 0.2 mm clearance on +12V
(acceptable for the design's 12 V / sub-amp load, may need
review if the load grows)
Snapshot the PDF and SVG exports plus ERC report for the standalone
TPS61088 boost reference schematic used as the integration source.
Confidence: high
Scope-risk: narrow
Snapshot the post-boost-integration design outputs: BOM CSV, schematic
PDF and SVG exports, and the ERC report against the current schematic.
Confidence: high
Scope-risk: narrow
Directive: These are regenerated outputs - refresh them when the schematic changes
Capture ERC outputs from the incremental schematic-build test harness used
during boost integration: per-feature slices (bins, junctions, labels,
no-connects, symbols 0-21, texts, wires) and cumulative/incremental runs.
The generating script lives in __pycache__ only (gitignored); these
reports document which slices were ERC-clean at integration time.
Confidence: medium
Scope-risk: narrow
Capture the working test schematics produced while iterating on the
boost-converter integration: firstpcb_test through firstpcb_test5 plus
firstpcb_a3 (A3 sheet variant) and firstpcb_nolib (stand-alone copy
with no external lib references). Includes ERC reports for the first
three test variants.
Confidence: medium
Scope-risk: narrow
Directive: These are exploration artifacts, not the production design - do not edit; treat as historical references
Drop 24 stale Feb-Mar snapshots and add today's 29 KiCad autosave zips
produced during the boost-converter integration session.
Confidence: high
Scope-risk: narrow
Open and save the board, project, and project-local state files under
KiCad 10. Bumps board format version 20241229 -> 20260206 with the new
tenting/covering/plugging/capping/filling stackup directives, drops the
removed HPGL plot params, and adds the KiCad 10 schema additions to the
project file (component class settings, IPC-2581 revision fields, ERC
rule keys, tuning-profile DRC keys, netclass meta version 5). Also
captures live editor UI state (active layer, column widths, hierarchy
collapsed list) in the .kicad_prl.
Constraint: Project is now opened with KiCad 10 - cannot be downgraded
Confidence: high
Scope-risk: broad
Directive: Do not edit these files with KiCad 9.x - format is one-way
Replace the 3-pos MaiXu MX126-5.0 terminal block footprint on the power
input connector with a 3-pos JST EH vertical header, matching the actual
battery harness. Namespace the RHL0020A footprint reference as
Project:RHL0020A so it resolves through the project-local Project.pretty
library rather than the previous unqualified bare name.
Constraint: RHL0020A footprint lives in the project-local library
Confidence: high
Scope-risk: narrow
Ignore KiCad lock files, the regenerated fp-info-cache, Python bytecode,
and editor/tooling local state (.history, .omc). Delete the previously
tracked fp-info-cache since KiCad regenerates it from the active library
tables on demand.
Confidence: high
Scope-risk: narrow
Previously fp-lib-table only contained a project-local Library.pretty entry
and sym-lib-table only contained the TPS61088 symbol library, which made
the project unable to resolve standard KiCad footprints/symbols on this
machine. Repopulate both tables with the full KICAD10 standard library
set, and add a project-local "Project" footprint library so footprints
like RHL0020A can be referenced via the Project: prefix.
Constraint: KiCad 10 uses KICAD10_FOOTPRINT_DIR/KICAD10_SYMBOL_DIR env vars
Confidence: high
Scope-risk: narrow
Add complete 5V-to-12V boost converter reference design around U2
(TPS61088QRHLRQ1) matching U1's circuit: input caps, compensation
network, soft-start cap, inductor, bootstrap cap, output caps, and
feedback voltage divider. Fix SW/BOOT pin types from power_in to
passive to resolve ERC errors. Update sym-lib-table to point to the
Q1 variant symbol library.
Constraint: Pin types must match U1's passive designation for SW/BST
Rejected: Leaving SW/BOOT as power_in | causes ERC "not driven" errors
Confidence: medium
Scope-risk: moderate
Not-tested: full ERC pass with both U1 and U2 present
Replace THT resistor footprints with 0805 SMD, assign 0805 caps for
small values, 1206 for 22uF bulk caps, SMD electrolytic for C3, Bourns
SRR1260 for L1, and QFN-20 for U1 TPS61088.
Remove the L7805 linear regulator (12V→5V) and its input/output caps,
replacing it with a TPS61088 boost converter circuit (5V→12V) for the
A4988 stepper driver. The ESP32 is now powered directly from the 5V
input rail. Includes integration script and project sym-lib-table for
the custom TPS61088 symbol library.
Python generator script produces a KiCad 9 schematic for the TPS61088
boost converter circuit (5V input, 12V/2A output) with feedback divider,
compensation network, bootstrap cap, and input/output filtering.
Includes a nix flake for the build environment.
Extend board outline downward by 15mm to accommodate 6 new components:
U1 (L7805 voltage regulator), C1/C2/C3 (decoupling caps), R1/R2 (pull-down
resistors). Move bottom mounting holes to match new outline. Delete
incorrectly-routed traces for DIR, STEP, LIM_C and unconnected nets, then
re-route them correctly to ESP32 bottom-row pins. Add +5V and +12V power
traces on B.Cu with via for layer transition. Route MOTOR_CTRL on B.Cu to
avoid F.Cu conflicts.
Place U1, C1, C2, C3, R1, R2 in the left open area (x=73-86, y=48-60)
of the board outline. Add copper traces for +12V bus (U1 input to
existing +12V net via A4988), +5V bus (U1 output to ESP32 VIN and C2),
and limit switch signals (/LIM_A to SW1, /LIM_C to existing trace).
Remove orphaned net-0 segments and clear zone fills for regeneration.
- Move regulator section labels (U1, C1, C2) to non-overlapping positions
- Hide redundant A4988 value text and R1/R2 GND value text
- Shift +3.3V, +12V, and GND power labels for better spacing
- Move C3, R1, R2 reference/value text away from nearby labels
- Add LM7805 (TO-220) with input/output caps to step 12V→5V for ESP32 VIN
- Add 10K pull-down resistors on D5/LIM_A and D4/LIM_C limit switch GPIOs
- Add 100uF electrolytic decoupling capacitor on A4988 VMOT
- Rewire A4988 ~ENABLE from GND to ESP32 D18 via MOTOR_EN net label
Remove all 60 point-to-point wires and 11 junctions. Replace with:
- 13 local power symbols (+3.3V, +12V, GND) at each power pin
- 10 net labels (STEP, DIR, LIM_A, LIM_C, MOTOR_CTRL) for signals
- 37 short stub wires connecting pins to labels/power symbols
- 4 direct wires for A4988 motor outputs to stepper connector
Electrical connectivity is preserved. No component positions changed.
Shift all 30 pins uniformly by +5.765mm to place bottom pins at
Y=37.2, exactly 5.8mm from the silkscreen bottom line. Adjust
silkscreen, fab, and courtyard bottom edges to Y=43/43.1. Pins
maintain their relative 2.54mm spacing.
Stretch bottom boundary from Y=37.235 to Y=43.92 so the footprint
spans 51mm from antenna top to USB-C end. Update silkscreen,
courtyard, and fab outlines accordingly. Also fix broken right-side
silkscreen line endpoint.
Move pin columns from 22.86mm to 25.4mm X spacing. Shift all pins
up by 4.125mm so bottom pins sit 5.8mm from the footprint bottom
boundary. Update silkscreen, courtyard, and fab outlines to match.
0xWheatyz
